Current Issue : October - December Volume : 2018 Issue Number : 4 Articles : 5 Articles
In order to simplify the hardware design and reduce the resource requirements, this paper\nproposes a novel implementation of a convolutional auto-encoder (CAE) in a field programmable\ngate array (FPGA). Instead of the traditional framework realized in a layer-by-layer way, we designed\na new periodic layer-multiplexing framework for CAE. Only one layer is introduced and periodically\nreused to establish the network, which consumes fewer hardware resources. Moreover, by fixing the\nnumber of channels, this framework can be applicable to an image of arbitrary size. Furthermore,\nto effectively improve the speed of convolution calculation, the parallel convolution method is used\nbased on shift registers. Experimental results show that the proposed CAE framework achieves good\nperformance in image compression. It can be observed that our CAE framework has advantages\nin resources occupation, operation speed, and power consumption, indicating great potential for\napplication in digital signal processing....
Taking inspiration from biology to solve engineering problems using the organizing\nprinciples of biological neural computation is the aim of the field of neuromorphic engineering.\nThis field has demonstrated success in sensor based applications (vision and audition) as well as in\ncognition and actuators. This paper is focused on mimicking the approaching detection functionality\nof the retina that is computed by one type of Retinal Ganglion Cell (RGC) and its application to\nrobotics. These RGCs transmit action potentials when an expanding object is detected. In this work\nwe compare the software and hardware logic FPGA implementations of this approaching function\nand the hardware latency when applied to robots, as an attention/reaction mechanism. The visual\ninput for these cells comes from an asynchronous event-driven Dynamic Vision Sensor, which leads\nto an end-to-end event based processing system. The software model has been developed in Java,\nand computed with an average processing time per event of 370 ns on a NUC embedded computer.\nThe output firing rate for an approaching object depends on the cell parameters that represent the\nneeded number of input events to reach the firing threshold. For the hardware implementation, on a\nSpartan 6 FPGA, the processing time is reduced to 160 ns/event with the clock running at 50 MHz.\nThe entropy has been calculated to demonstrate that the system is not totally deterministic in response\nto approaching objects because of several bioinspired characteristics. It has been measured that a\nSummit XL mobile robot can react to an approaching object in 90 ms, which can be used as an\nattentional mechanism. This is faster than similar event-based approaches in robotics and equivalent\nto human reaction latencies to visual stimulus....
In this paper, we propose a field programmable gate array (FPGA) implementation of a\none-dimensional convolution neural network (1D-CNN) demodulator for binary phase shift keying\n(BPSK). The 1D-CNN demodulator includes two 1D-CNNs and a decision module. Discrete time\nseries of BPSK signals are imported into the well-trained 1D-CNNs. The 1D-CNNs detect the phase\nshiftsââ?¬â?¢ moment and type, including phase shift from 0 to Ãâ?¬ and that from Ãâ?¬ to 0. The decision module\ncombines results of the two 1D-CNNs and outputs the demodulated data. In order to improve the\nefficiency of resource utilization and operation speed of the FPGA circuit, a time-delay network for\nconvolutional calculation and a structure for piecewise approximation for the activation function\nwere designed. To enhance the performance of the 1D-CNN demodulator, universal and diversity\ntraining data considering five impact factors were generated specially. Experimental results under\ndifferent channel conditions show that the proposed demodulator has good adaptability to frequency\noffset and short latency. The demodulation loss of the proposed demodulator can almost be kept\nwithin 2 dB....
Digital cross-correlation is central to many applications including but not limited to Digital\nImage Processing, Satellite Navigation and Remote Sensing. With recent advancements in digital\ntechnology, the computational demands of such applications have increased enormously. In this paper\nwe are presenting a high throughput digital cross correlator, capable of processing 1-bit digitized\nstream, at the rate of up to 2 GHz, simultaneously on 64 channels i.e., approximately 4 Trillion\ncorrelation and accumulation operations per second. In order to achieve higher throughput, we\nhave focused on frequency based partitioning of our design and tried to minimize and localize high\nfrequency operations. This correlator is designed for a Passive Millimeter Wave Imager intended for\nthe detection of contraband items concealed on human body. The goals are to increase the system\nbandwidth, achieve video rate imaging, improve sensitivity and reduce the size. Design methodology\nis detailed in subsequent sections, elaborating the techniques enabling high throughput. The design\nis verified for Xilinx Kintex UltraScale device in simulation and the implementation results are given\nin terms of device utilization and power consumption estimates. Our results show considerable\nimprovements in throughput as compared to our baseline design, while the correlator successfully\nmeets the functional requirements....
The conversion and control for the utilization of power generated from energy sources can\nbe performed using a power electronic converter system. The voltage source inverter (VSI) is one of\nthe commonly used converter topologies, being controlled by a switching control algorithm for power\nconversion. Finite set-model predictive control (FS-MPC) is a modern switching control algorithm\nand has received significant attention due to its predictive nature. In this paper, the implementation\nof FS-MPC is presented for the load-side current control of a three-phase VSI system using an\nintegrated platform of MATLAB/Simulink and Xilinx system generator (XSG). The XSG provides the\nfunctionality of digital design and intuitive implementation of field-programmable gate array (FPGA)\ncontrolled systems. The additional functionality of hardware-in-the-loop (HIL) co-simulation using\nFPGA is used for the testing and validation of controller performance. The controller performance is\nvalidated through three platforms: MATLAB/Simulink, XSG and HIL co-simulation using ZedBoard\nZynq evaluation and development FPGA kit....
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